In recent years, with the advance of miniaturization of a cellular phone, a demand for miniaturization of a camera module to be mounted on the cellular phone has been increasing. In order to satisfy the demand, application of a through-electrode technique and an increase in integration density of a sensor chip have been planned.
For example, when rewiring is performed on a rear surface side of an imaging semiconductor element by using a through-electrode to form a solder ball terminal, a camera module smaller than that obtained by using conventional wire bonding can be formed (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2006-32699).
In this case, an electrode pad portion to which the through-electrode is connected is desired to be flat. When a semiconductor substrate on which an imaging element is formed is viewed from a first major surface side of the semiconductor substrate, the electrode pad to which the through-electrode is connected is a rectangular or square flat film. A through-hole is formed from a second major surface side of the semiconductor substrate to the electrode pad. Thereafter, the through-electrode is formed on the electrode pad and in the through-hole.
On the other hand, with the increase in degree of integration of a sensor chip, a copper (Cu) interconnection has been used to reduce an interconnection resistance of an LSI. A vapor pressure of a copper halide is low, and dry etching of copper cannot be easily performed. For this reason, unlike in aluminum interconnection, a process in which, after a metal film is formed on an entire surface, the metal is processed into an interconnection shape by reactive ion etching (RIE) cannot be used. For this reason, a copper interconnection is assumed to be a buried interconnection, and must be processed by the chemical mechanical polishing (CMP) technique. However, as in an electrode pad, when CMP is performed to a large-size copper pattern, amounts of polishing are different from each other in the copper pattern to disadvantageously cause dishing.
Therefore, when a through-electrode is connected to an electrode pad comprising copper, the electrode pad has a pattern in which copper-free regions are arranged at predetermined intervals. In order to cause the through-electrode to penetrate to the electrode pad, a silicon substrate is etched. Thereafter, an interlayer insulating film on a rear side of the electrode pad is etched.
Etching is performed for a time longer than an arithmetically obtained time (overetching) to eliminate a difference in etching amounts over an entire region on a wafer plane and reliably form a hole to an electrode pad. Since the electrode pad has a pattern with a net-like copper-free region or rod-like copper-free regions, oxide films present in the free regions between the electrode pads are excessively etched, and a large step is formed between an electrode pad portion and an oxide film portion.
Thereafter, a barrier metal and seed copper are sputtered in the through-hole to form a through-electrode, and copper is plated by electrolytic plating. In this case, if a large step is present between the electrode pad portion and the oxide film portion, the barrier metal and the seed copper are not sufficiently formed, and a void occurs upon copper plating. In this manner, when the void occurs between the electrode pads, the through-electrode is deteriorated in reliability.